Title: System and method for manipulating an integrated circuit layout

Document Type and Number: United States Patent 7222321

Abstract:  system and method for manipulating an integrated circuit layout allowing for reuse and migration. The method comprises steps of identifying objects in a geometric layout to generate a first symbolic layout, nesting a plurality of objects in the first symbolic layout to generate a first virtual device, and associating the first virtual device to generate a second symbolic layout. The method further comprises a step of modifying parameters and constraints of the first virtual device to generate a third virtual device, and a step of optimizing a second symbolic layout including the first virtual devices to generate a third symbolic layout based on the third virtual device. Consequently, the second symbolic layout can be reused. Further, the method comprises a step of updating parameters and constraints of the first virtual device based on new process rules to generate a fourth virtual device so that the second symbolic layout can be used to generate a third symbolic layout for migration.

Inventors: Lin, Po-Huang (HsinChu, TW),  Su, Yi-Jen (HsinChu, TW),  Shih, Ming-Chih (HsinChu, TW)

Application Number: 11/125,168

Filing Date: 05/10/2005

Publication Date: 05/22/2007

Assignee: Anaglobe Technology, Inc (HsinChu, TW)

Representative Image:

Primary Examiner: Dinh, Paul

Assistant Examiner: Parihar, Suchin

Attorney, Agent or Firm: Volentine & Whitt, PLLC

Claims: What is claimed is:

1. A method for manipulating an integrated circuit layout, comprising: receiving a geometric layout; identifying primitive objects in the geometric layout to generate a first symbolic layout based on a technology file; nesting a plurality of primitive objects to generate a first virtual device in the first symbolic layout; associating the first virtual device to generate a second symbolic layout; adding additional primitive objects to the first virtual device to generate a second virtual device after associating the first virtual device; associating the second virtual device; modifying parameters and constraints of the first virtual device to generate a third virtual device; updating parameters and constraints of the first virtual device based on rules of a new fabrication process to generate a fourth virtual device; optimizing the second symbolic layout including the first virtual device to generate a third symbolic layout based on the fourth virtual device; and adding constraints to the fourth virtual device.
2. The method for manipulating an integrated circuit layout of claim 1, further comprising extracting primitive object models from a layer information that is stored in the technology file.
3. The method for manipulating an integrated circuit layout of claim 2, wherein said identifying primitive objects in the geometric layout is based on the primitive object models.
4. The method for manipulating an integrated circuit layout of claim 2, wherein said extracting primitive object models from layer information that is stored in the technology file comprises categorizing the layer information based on properties of the layer information.
5. The method for manipulating an integrated circuit layout of claim 1, further comprising adding parameters to the first virtual device.
6. A method for manipulating an integrated circuit layout, comprising: receiving a geometric layout; identifying primitive objects in the geometric layout to generate a first symbolic layout based on a technology file; nesting a plurality of primitive objects to generate a first virtual device in the first symbolic layout; and associating the first virtual device to generate a second symbolic layout, wherein said identifying primitive objects in the geometric layout comprises extracting primitive object models from layer information that is stored in the technology file, and wherein said extracting primitive object models from layer information that is stored in the technology file comprises categorizing the layer information based on properties of the layer information.

Copyright (c) 2004 AnaGlobe Technology, Inc. All rights reserved